Scan Chain Insertion

-

 

All the flip-flops present in the design are replaced with the scan flip-flops (for a full scan design). The scan flip-flops are connected together in form of a chain so we call it as a scan chain. Scan chain acts as a shift register when the design is in test timing mode, Then Scan_EN (test enable signal) is active high. The first flip-flop of the scan chain is connected to the scan input port and the last flop the scan chain is connected to the scan_op scan output.

When some of the flip-flops are intentionally not converted to scan flops, such designs are called partial scan design. Making a design full scan makes the design more testable for manufacturing defects at the cost of complexity, area and power.

There are three stages of scan chain operation




          
                          

Comments

Post a Comment

Popular posts from this blog

KEEPOUT MARGIN

-
Image
  Keepout margin : This the one of the technique using during placement macros and standard cells in the core area. It is the region around the boundary of fixed cells in a block in which no other cells are placed. The width of the keep-out margin on each side of the fixed cell can be the same or different. Keeping the placement of cells, macros etc.. This technique can  avoids congestion and nets detouring and timings. For the best quality of results. How we decide the margin?  The margin is decided based on the macros or IPs .These macros and IPs will come from vendors its clearly mention in the document regarding the margin around the macros like expected values will be mentioned, by reading the document we can get the values will giving the values we may increase or decrease depend on the problem we faced in the core area. For the std cells, basically we will keep out margin to mainly for AOI ,IOA and Multibit flops etc. Why only AOI, IOA and multibit flops because these cells will
Read more

ZWL(Zero Wire Load) Why its preferred ?

-
Image
  1) If we provide the Wire details prior to PNR stage then its called wire load Module. ( so we will  provide parasitic information file to the tool) 2) But coming to ZWL we wont provide any wire information to the tool so tool will assume that wire is zero ( we will not provide any parasitic information to the tool). Then how will tool will estimate the parasitic information? so tool will understand that net delay is zero, While checking the Timing from the tool, The tool will pick the cell  net delay from the standard cell libraries. Now we got the extract timing information with respective the standard cells used in the design.  Then how it will be helped in the timing? if you check in the tool by providing with and without parasitic information file you will differ with respective setup time and hold time of a chip.  By doing some analysis with ZWL timing will be clean in setup and hold is under control across the corners. Run time is also fast and implementation time will be less
Read more