SKR_VLSI

  All the flip-flops present in the design are replaced with the scan flip-flops (for a full scan design). The scan flip-flops are connected together in form of a chain so we call it as a scan chain. Scan chain acts as a shift register when the design is in test timing mode, Then Scan_EN (test enable signal) is active high. The first flip-flop of the scan chain is connected to the scan input port and the last flop the scan chain is connected to the scan_op scan output. When some of the flip-flops are intentionally not converted to scan flops , such designs are called partial scan design. Making a design full scan makes the design more testable for manufacturing defects at the cost of complexity, area and power. There are three stages of scan chain operation                                      

  Keepout margin : This the one of the technique using during placement macros and standard cells in the core area. It is the region around the boundary of fixed cells in a block in which no other cells are placed. The width of the keep-out margin on each side of the fixed cell can be the same or different. Keeping the placement of cells, macros etc.. This technique can  avoids congestion and nets detouring and timings. For the best quality of results. How we decide the margin?  The margin is decided based on the macros or IPs .These macros and IPs will come from vendors its clearly mention in the document regarding the margin around the macros like expected values will be mentioned, by reading the document we can get the values will giving the values we may increase or decrease depend on the problem we faced in the core area. For the std cells, basically we will keep out margin to mainly for AOI ,IOA and Multibit flops etc. Why only AOI, IOA and multibit flops because these cells will

  Clock skew Arrival time of the clock Transition or Difference in clock arrival time at two spatially distinct points (TCLK1 and TCLK2) positive skew if the capture clocks comes late than launch clock then its called +skew +skew can lead to hold violations Negative skew if the capture clock comes early than launch clock it is called -skew -skew can lead to setup violations Useful skew it is a concept of delaying the capturing flop clock path this approach will helps in meeting setup requirements. setup requirement with in the launch and capture timing path. But the hold requirement has to be met for the design. Useful skew techniques can be used to fix both setup and hold violations. One disadvantage of this technique is that if the design has multiple modes of operation, then useful skew can potentially cause a problem in another mode.

 

 

 

                                                                Inverter                                                                             Layout Transient Response

  Advantage: Its very small skew Disadvantage : The time that spread from the clock root to the global mesh is basically the same, the time that spread from the global mesh to each local tree register is different and clock mesh structure consumes more routing resources hence redundant interconnect structure will bring more power consumption.

  Advantages : it makes easy to reduce the skew Disadvantage : It effect the process parameters and problem with Phase delay

  Advantages: Its easy to adjust the capacitance of driving net to better achieve of SKEW requirement Disadvantages : But DUMMY cells used to balance the load it leads to increases power and area

  H-Tree Advantage: It is easy to reduce clock skew Disadvantage: Difficult to fix register placement

  This pic from smartplay

 

 

  Synthesis Inputs: ·        RTL netlist [.v or.vhdl] ·        .lib [liberty Timing File] ·        .lef [library exchange formate] ·        SDC [synopsys Design constraints]

 

 

  DESIGN ENGINEER COURSE CONTENT Introduction to Physical Design Flow & Inputs         Synthesis Design Planning (Floor-plan) Operating Conditions (PVT) Static timing Analysis Pre placement &Std-Cell Placement Cts & Post Cts Optimization Routing Sign-off Checks Timing Closure & ECO Implementatio n