SDC main checks for chip/block level.

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1 Clock Definitions : unclocked flops and Clocks defined on hierarchical pins

2 IO delays: unconstraint's input and output delays, and any conflicts constant value to the same pins

3 set_case_analysis: any signal values with different enable signal

4 clock to clock false path : Missing timing exceptions between clocks with non-integer clock periods.

5 Generated clocks : Clocks not defining the master clock


The engineer needs to check the clock definitions, clock groups, synchronous relationships, 
or even mode info about the design; which is again all available in well made SDC files.  
In fact if SDC is done right then major issues can solve in complete chip level or block level
 it lets you automatically create high quality setup files many other downstream tasks and tools.

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