Clock- gating to optimize the leakage and dynamic power

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From the above gating circuit using MUX for data diagram the clocking strategy safeguard that the flop updates every clock cycle even though the data (d) signal is valid when the enable line goes high. mainly the number of clock cycles are wasted, so to over the above problem we are inserting the AND gates instead of mux. (you use any gate not only AND gate).


We can optimize the circuit above for power consumption ensuring that the flop is clocked only when the data (d) line is validated with the enable signal.


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