SKR_VLSI

1 Clock Definitions : unclocked flops and  Clocks defined on hierarchical pins 2 IO delays: unconstraint's input and output delays, and any conflicts constant value to the same pins 3 set_case_analysis: any signal values with different enable signal 4 clock to clock false path :  Missing timing exceptions between clocks with non-integer clock periods. 5 Generated clocks : Clocks not defining the master clock The engineer needs to check the clock definitions, clock groups, synchronous relationships, or even mode info about the design; which is again all available in well made SDC files. In fact if SDC is done right then major issues can solve in complete chip level or block level it lets you automatically create high quality setup files many other downstream tasks and tools.

  In order to over the timing problem, while inserting the clock gating, we need to insert the clock gating at the correct  position such that it should not effect the timing. Even if we the  add the ICG for every flop it leads to more dynamic power  For example ICG cloning will be happened for every 20 flops  again depends on Technology.

  From the above gating circuit using MUX for data diagram the clocking strategy safeguard that the flop updates every clock cycle even though the data (d) signal is valid when the enable line goes high. mainly the number of clock cycles are wasted, so to over the above problem we are inserting the AND gates instead of mux. ( you use any gate not only AND gate ). We can optimize the circuit above for power consumption ensuring that the flop is clocked only when the data (d) line is validated with the enable signal.

  AOCV (ADVANCE ON_CHIP_VARITIONS)   Aocv will be calculated with the depth and distance by seeing above figure you will get an idea. for the above figure we will consider depth as 6 because path-1 is the longest path from the above fig. so tool will take the depth as 6 from the aocv file and distance is calculated with the help of will the diagonal distance. But AOCV will be calculated from the diverging point only. Note: just understanding purpose I kept buffer in the above diagram in place of buffers it may gates flops etc.. AOCV setting can be done on both PNR tools and STA tools. While doing analysis we will flow some time Graph based Analysis and Path based Analysis both  With the help of AOCV we will get 3 to 4% of pessimism   lets see some difference between GBA and PBA GBA it will have worst skew (transitions) its not realistic  fast analyzer less memory required worst aocv derating will occurs.. etc  PBA Actual skew will be propagated its more realistic  slow analyzer more m

                                                        Above high                                                                                                                      Above low                                    Below low                                                                                                                         Below high Beyond the rails these are more critical part the block if its occurs there is high possibility of gate demands Between the rails will have the power model files like ccs NLPM, etc., depends on the technology To avoid Beyond the rails effect in the block: For these beyond the rails first we will do some reliability checks then after will give some margin. which is not the part of the noise models  margin setting will done manually for this models with the help of set_noise_margin command How much margin ? Its again depends upon the gate withstand effect  which will comes from foundry  its generally 30 to 40% of vdd.