ZWL(Zero Wire Load) Why its preferred ?
1) If we provide the Wire details prior to PNR stage then its called wire load Module. ( so we will provide parasitic information file to the tool) 2) But coming to ZWL we wont provide any wire information to the tool so tool will assume that wire is zero ( we will not provide any parasitic information to the tool). Then how will tool will estimate the parasitic information? so tool will understand that net delay is zero, While checking the Timing from the tool, The tool will pick the cell net delay from the standard cell libraries. Now we got the extract timing information with respective the standard cells used in the design. Then how it will be helped in the timing? if you check in the tool by providing with and without parasitic information file you will differ with respective setup time and hold time of a chip. By doing some analysis with ZWL timing will be clean in setup and hold is under control across the corners. Run time is also fast and implementation time will be less